Design and analysis of degradation-hard integrated circuits

With the decrease of the gate oxide thickness and increase of the electric fields, generation of hot carriers is a problem in current-day CMOS circuits. The resulting transistor degradation limits the circuit lifetime and thus needs to be analyzed and calculated during the design of the circuit. Starting from the degradation model of a single transistor, the degradation of circuit blocks is examined. This comprises different aspects, going from the model used for the degradation over the method used for simulating it to the extraction of design rules for obtaining a degradationhard design. In cooperation with an industrial chip designer, a set of design rules has been extracted and a verification tool for checking the design prior to manufacture has been developed. The application of the design method and verification tool has been checked on two example blocks which have been designed, manufactured and measured. Keywords—Analog integrated circuits, hot carrier degradation, design methodology